1. Field of the Invention
The present invention relates to an offset-voltage calibration circuit, and more specifically, to an offset-voltage calibration circuit capable of calibrating an offset voltage having an unpredicted magnitude, calibrating an offset voltage of not only a comparator but also the entire circuit, and minimizing power consumption.
2. Discussion of Related Art
In recent years, with the development of complementary metal oxide semiconductor (CMOS) technology, the demand for comparators used for circuits capable of processing analog signals, such as analog-to-digital converters (ADCs), has increased. The comparators may be circuits configured to precisely compare the voltages of two signals having a minute voltage difference therebetween and output a comparison result.
In general, a conventional comparator may include a pre-amplifier and a latch, which are connected in cascade, to enable high-speed high-resolution operation. Since the pre-amplifier has a low offset voltage and the latch has a great voltage gain, the conventional comparator may have a combination of advantages of both the pre-amplifier and the latch, thereby increasing an operating speed and accuracy.
Meanwhile, comparators with various structures have been proposed to reduce the offset voltages of the comparators. However, offset caused by mismatching of devices, which may occur during CMOS processes, may be basically unavoidable. The offset may lead to malfunctions in circuits and deteriorate linearity and noise performance of ADCs using comparators.
FIG. 1 is a circuit diagram of a comparator to which a conventional offset removing technique is applied.
Referring to FIG. 1, a comparator to which an offset removing technique is applied may include a latch and a pre-amplifier, which are connected in cascade. The conventional comparator may have the following problems. First, since output signals output from output terminals outp and outn of a pre-amplifier are directly applied to the latch, a kick-back effect may be likely to occur due to a parasitic capacitance between gate and drain electrodes of a transistor. Second, since the magnitude of an offset voltage removed from the entire circuit depends on the magnitude of current IIN supplied to the comparator, the magnitude of the current IIN should be determined by predicting an offset voltage of the comparator. That is, since the current IIV is not varied, the magnitude of the current IIN to be supplied should be determined beforehand by predicting the offset voltage of the comparator. However, when a higher offset voltage than the predicted offset voltage is caused, calibrating the offset voltage may be impossible.
Also, a conventional offset calibration circuit may remove only an offset voltage of a comparator. That is, when the comparator is applied to a successive approximation register ADC (SAR ADC), only the offset voltage of the comparator may be calibrated, while an offset voltage caused by a digital-to-analog converter (DAC) may not be removed but affect operations of the offset calibration circuit.
Accordingly, it is necessary to develop an offset voltage calibration technique capable of calibrating an offset voltage also within an unpredicted range of offset voltages, calibrating an offset voltage of not only a comparator but also a DAC as an analog block in a circuit, such as an SAR ADC, and minimizing power consumption.